In some applications for manufacturing semiconductor devices it may be desirable to implement structures having smaller (shorter) dimensions, e.g. in MOS transistors (MOS=metal oxide semiconductor), e.g. LDMOS transistor (LDMOS=laterally diffused metal oxide semiconductor), the gate electrode or the gate oxide, respectively.
In the art, lithography methods are known by use of which (poly) gate electrodes are manufactured. These known methods are not self-aligning, so that limitations based on the limited alignment possibilities of the used illumination instruments result. The disadvantage of the thus manufactured gate structures is that a certain gate length may not be fallen short of and that certain tolerances may not be achieved.
It is a further disadvantage of the conventional methods that a different doping of source areas and drain areas, like it is for example required in an LDMOS transistor or a DMOS transistor, is only hardly possible or not at all possible with short gate structures.